1. Field of the Invention
The invention relates to the field of computer design and in particular to methods and apparatus for designing the communication protocol among a plurality of computer components of a system on a chip.
2. Description of the Prior Art
System-on-Chip (SoC) designs are becoming increasingly more complex, with more and more components being integrated into a single SoC design. Communication between these components is increasingly dominating critical system paths and frequently becomes the source of performance bottlenecks. It therefore becomes imperative for designers to explore the communication space early in the design flow. Traditionally, system designers have used pin-accurate Bus Cycle Accurate (PA-BCA) models for early communication space exploration. These models capture all of the bus signals and strictly maintain cycle accuracy, which is useful for exploration of the degree of reliable performance, but results in slow simulation speeds for complex designs, even when they are modeled using high level languages.
Recently there have been several efforts to use the Transaction Level Modeling (TLM) paradigm for improving simulation performance in BCA models. However, these transaction based BCA (T-BCA) models capture a lot of details that can be eliminated when exploring communication architectures.
SoC designs today have several components (central processing units (CPUs), digital signal processors (DSPs), memories, peripherals etc.) which share the processing load and frequently exchange data with each other. It therefore becomes imperative for system designers to focus on exploring the communication space quickly, reliably and early in the design flow to make the right choices and eliminate performance bottlenecks under time-to-market pressures.
Shared-bus based communication architectures such as AMBA, CoreConnect, WishBone and OCP are popular choices for on-chip communication between components in current SoC designs. These bus architectures can be configured in several different ways, resulting in a vast exploration space that is prohibitive to explore at the register transfer level (RTL) level. Not only is the RTL simulation speed too slow to allow adequate coverage of the large design space, but making small changes in the design can require considerable re-engineering effort due to the highly complex nature of these systems.
To overcome these limitations, system designers have raised the abstraction level of system models. FIG. 1 is a symbolic diagram which shows the frequently used modeling abstraction levels for communication space exploration, usually captured with high level languages such as C/C++. These high level models give an early estimate of the system characteristics before committing to RTL development. In Cycle Accurate (CA) models, system components (both masters and slaves) and the bus architecture are captured at a cycle and signal accurate level. While these models are extremely accurate, they are too time-consuming to model and only provide a moderate speedup over RTL models. Bus Cycle Accurate (BCA) models capture the system at a higher abstraction level than Cycle Accurate (CA) models. Components are modeled at a less detailed behavioral level, which allows rapid system prototyping and considerable simulation speed over RTL. The component interface and the bus however are still modeled at a cycle and signal accurate level, which enables accurate communication space exploration. However, with the increasing role of embedded software and rising design complexity, even the simulation speedup gained with BCA models is not enough.
Recent research efforts have focused on using concepts found in the Transaction Level Modeling (TLM) domain to speed up BCA model simulation. Transaction Level Models are very high level bit-accurate models of a system with specifics of the bus protocol replaced by a generic bus (or channel), and where communication takes place when components call read( ) and write( ) methods provided by the channel interface. Since detailed timing and signal-accuracy is omitted in TLM, these models are fast to simulate and are useful for early embedded software development and functional validation of the system. Transaction based BCA (T-BCA) models make use of the read/write function call interface, optionally with a few signals to maintain bus cycle accuracy. The simpler interface reduces modeling effort and the function call semantics result in faster simulation speeds. However these approaches do not fully exploit the potential for speedup when modeling systems for exploring on-chip communication tradeoffs and performance.
Since detailed timing and pin-accuracy is omitted in Transaction Level Models, these models are fast to simulate and are useful for early functional validation of the system. Others have also proposed a top-down system design methodology with four models at different abstraction levels. The architecture model in their methodology corresponds to the TLM level of abstraction while the next lower abstraction level (called the communication model) is a BCA model where the generic channel has been replaced by bit and timing accurate signals corresponding to a specific bus protocol.
Early work with TLM established SystemC 2.0 as the modeling language of choice for the approach. We have previously described how TLM can be used for early system prototyping and embedded software development. Others have defined a system level exploration platform for network processors which need to handle high speed packet processing. The SOCP channel described in their approach is based on OCP semantics and is essentially a simple TLM channel with a few added details such as support for split transactions. It has also been proposed that a component based bottom-up system design methodology be provided where components modeled at different abstractions are connected together with a generic channel like the one used in TLM, after encapsulating them with suitable wrappers. Commercial tools such as the Incisive Verification Platform, ConvergenSC System Designer and Cocentric System Studio have also started adding support for system modeling at the higher TLM abstraction, in addition to lower level RTL modeling.
Recently, research efforts have focused on adapting TLM concepts to speed up architecture exploration. Some researchers have used function calls instead of slower signal semantics to describe models of AMBA2 and CoreConnect bus architectures at a high abstraction level. However, the resulting models are not detailed enough for accurate communication exploration. Others have made a similar attempt to model AMBA2 using function calls for reads/writes on the bus, but also model certain bus signals and make extensive use of SystemC clocked threads which can slow down simulation. Researchers have also proposed model data transfers in AMBA2 using read/write transactions but use low level handshaking semantics in the models which need not be explicitly modeled to preserve cycle accuracy. Recently, ARM released the AHB Cycle-Level Interface Specification which provides the definition and compliance requirements for modeling AHB at a cycle-accurate level in SystemC. Function calls are used to replace all bus signals at the interface between components and the bus.
What is needed is an approach for a faster transaction-based modeling abstraction level (CCATB) to explore the communication design space.